M.E/M.Tech Applied Electronics Question banks for ECE
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M.E. DEGREE EXAMINATION, APRIL/MAY 2011
M.E. DEGREE EXAMINATION, APRIL/MAY 2011
First Semester
Applied Electronics
MA 9217 — APPLIED MATHEMATICS FOR ELECTRONICS ENGINEERS
(Common to M.E. VLSI Design)
(Regulation 2009)
Time : Three hours Maximum : 100 marks
Answer ALL questions
PART A — (10 × 2 = 20 marks)
= ,7.0 b = 6.0 .
3. Define Pseudo inverse of a full rank matrix A.
4. Define Toeplitz matrix and give an example.
5. Find the moment generating function of the random variable whose moments
are r
.2)!1( r
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Reg. No. :M.E. DEGREE EXAMINATION, NOVEMBER/DECEMBER Elective 2010
Applied Electronics
AP 9251 — DIGITAL IMAGE PROCESSING
(Common to M.E. Communication Systems)
(Regulation 2009)
Time : Three hours Maximum : 100 Marks
Answer ALL questions
ART A — (10 × 2 = 20 Marks)
1. State 2D sampling theorem.
2. What is meant by dither?
3. What is the advantage is Walsh transform over Fourier transform?
4. List the properties of Haar transform.
5. What is median filtering? State its properties.P
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Reg. No. :J7603
M.E. DEGREE EXAMINATION, JUNE 2010
First Semester
vantages of segmented memory?
2. Mention the different types of pipeline hazards.
3. What is the system memory management mode of operation for the Pentium?
How is the mode exited?
4. What are the limitaApplied Electronics
AP9213 — ADVANCED MICROPROCESSORS AND MICRO CONTROLLERS
(Common to M.E. Communication Systems and M.E. VLSI Design)
(Regulation 2009)
Time : Three hours Maximum : 100 Marks
Answer ALL Questions
PART A — (10 × 2 = 20 Marks)
1. What are the adtions of paging mechanism?
5. List the most notable features of the ARM instruction set.
6. Define the pipeline stages in a 5-stage pipeline of ARM processor.
7. List the different types of addressing modes supported by Motorola 68HC11.
8. What are the built-in peripherals in 68HC11?
9. Show the status register format in PIC micro controller.
10. Name the different interrupt sources present in PIC micro controller.
Or address 0 mapping 1 techniques used 4 in cache (16)
(i) Explain the technique used to minimize hazards in a pipeline processor. (10)
(ii) Compare RISC and CISC processor architectures. (6)
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