If any add appear like this please click skip add
Showing posts with label ECE FOURTH. Show all posts
Showing posts with label ECE FOURTH. Show all posts
Sunday, November 4, 2012
EE2254 — LINEAR INTEGRATED CIRCUITS AND APPLICATIONS question papers with solution four years huge collection
Tags:LINEAR INTEGRATED CIRCUITS, ECE FOURTH, ANNA UNIVERSITY QUESTION BANKS FOR ECE, EEE, EEE FOURTH, EEE THIRD, anna university question bank for eee, QUESTION PAPERS, QUESTION BANKS,
Tuesday, September 11, 2012
Anna university Revaluation Results for 2nd,4th ,6th semster
Dear Prof/Stud
Anna university is going to release the second fourth and sixth semester revaluation results by the end of September last week or begin of October.This time paper valuation is moderate only.So Stud/Prof dont expect much thing.But We pray with god everyone will get good marks.All the best for your results.And Concentrate well on this current semester do well.God Always with you.
To Get Results in your inbox
Click all the following links and activate it.We are No 1 to send the results to students inbox.
Have a great future. All the best for final year students who are all preparing for placements
LINK 1 for results toolbar in your browser
LINK 2 for results to inbox
LINK 4 click here for official node
When will the results for even semester ?
Which site will publish results ?
How will be the revaluation of 2nd,4th,6th semester ?
Anna university Revaluation Results for 2nd,4th ,6th semster?ALL RESULTS, how to apply revaluation for anna university B.E/B.Tech, ALL DEPT, Anna University, HOW TO, ECE, ECE FOURTH, ECE SEVENTH, ECE SECOND, CSE THIRD, EEE THIRD,
Regards
Geek University Members
Wednesday, August 1, 2012
ANNA UNIVERSITY 2ND 4TH 6TH AND 8TH SEMESTER RESULTS PUBLISHING SITE UPDATED |WHEN WILL BE THE ANNA UNIVERSITY RESULTS FOR 4TH SEMESTER AND 6TH SEMESTER
ANNA UNIVERSITY MAY/JUNE 2012 RESULTS | 2ND,4TH,6TH|
Anna University Result for arrear students - 8th Semester
Exam Results 2012 | Exam Results India | Results Website
Anna University Results 2012 8th, 2nd, 4th, 6th Semester May/June
Anna University Results 2012, Chennai Results May / June 2012
Anna University Results 2012 | UG Results | PG Results | Exam
Anna University Result for arrear students - 8th Semester
ANNA UNIVESITY 4 TH AND 6TH SEM RESULTS PUBLISHING SITE UPDATED
WHEN WILL BE THE ANNA UNIVERSITY RESULTS FOR 4TH SEMESTER AND 6TH SEMESTER
Anna University Results 2012 8th, 2nd, 4th, 6th Semester May/June Result 2012 : 1.Anna University 2nd, 4th, 6th, 8th semester may, june results 2012 will be declared. candidates can easily check out their anna university result 2012.
2.According the Anna University will be Declared the results may / june 2012 of 2nd, 4th, 6th, 8th semester Examiantion results 2012 will published on official web site
@ www.annauniv.edu
@ http://results.chennaieducation.net/annauniv/
Friday, May 11, 2012
MICROPROCESSORS AND MICRO CONTROLLER 2012
Anna University Examination May/June 2012 Important Questions EE2354 - MICROPROCESSOR MICROCONTROLLER Unit I 1.Discuss in detail about the minimum and maximum mode of operation of 8086 with neat diagram 2.Explain in detail about Pin configuration of 8085 processor with neat diagram 3. Discuss in detail about the types of interrupts in 8086? Explain each in detail 4. Explain with the help of neat diagram interfacing of RAM and ROM memory device with 8085 microprocessor with an example Unit II 1. Explain in detail about the functions of various data transfer and arithmetic instructions of 8085 2.Explain the addressing modes of 8085 and 8086 with an example. 3. Write an assembly language program in 8085 to find the maximum number from the given n numbers , sorting n elements in an array 4. Explain the functions of various branch and machine control instructions of 8085 With suitable examples Unit III 1.Explain the operation and programming of 8251 USART in detail. 2.Explain the ADC interfacing with 8085 microprocessor with Neat Diagram 3. Explain the different modes of operation and draw the functional block diagram of 8254 timer 4.Draw the block diagram to interface 8085 microprocessor with A/D converter and D/A converter Unit IV 1.Discuss about the organization of internal RAM and special function registers of 8051 microcontroller. 2.Draw the pin diagram of 8051 microcontroller and explain it in detail 3.Explain the interrupt structure with associated register in 8051 microcontrollers 4.Explain in detail about architecture and various operating modes of 8255 PPI. Unit V 1.Explain in detail about all blocks and how 8051 is used in washing machine control. 2.Explain with program to rotate the stepper motor in both clockwise and anticlockwise direction using 8051 microcontroller 3.Explain in detail how DAC and 8-bit ADC interfaced with 8051 micro controller 4.Discuss in detail about the addressing modes of 8051 microcontroller and brief advantages of using a microcontroller instead of micro processor
Wednesday, May 9, 2012
DIGITAL LOGIC CIRCUITS QUESTION BANKS FOR EEE
anna university question bank for eee, EEE FOURTH,DIGITAL LOGIC CIRCUITS, QUESTION BANKS, ANNA UNIVERSITY QUESTION BANKS FOR ECE, ECE FOURTH, EEE, ECE,
click here to get full Download
DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING
DIGITAL LOGIC CIRCUITS
YEAR : II
SEMESTER : IV
UNIT - I
BOOLEAN ALGEBRA & COMBINATIONAL CIRCUITS
PART-A
1) What is meant by parity bit?
2) What are registers?
3) What is meant by register transfer?
4) Define binary logic?
5) Define logic gates?
6) Define duality property.
7) State De Morgan’s theorem.
8) Reduce A.A’C.
9) Reduce A (A + B).
10) Reduce A’B’C’ + A’BC’ + A’BC.
11) Reduce AB + (AC)’ + AB’C (AB + C).
12) Simplify the following expression Y = (A + B) (A + C’) (B’ + C’).
13) Simplify the following using De Morgan’s theorem.
14) Show that (X + Y’ + XY) (X + Y’) (X’Y) = 0.
15) Prove that ABC + ABC’ + AB’C + A’BC = AB + AC + BC.
16) Convert the given expression in canonical SOP form Y = AC + AB + BC.
17) Convert the given expression in canonical POS form Y = (A + B)(B + C)(A + C).
18) Find the minterms of the logical expression Y = A’B’C’ + A’B’C + A’BC + ABC’
20) Write the maxterms corresponding to the logical expression Y = (A + B + C’)
21) Convert (4021.2)5 to its equivalent decimal.
22) What are called don’t care conditions?
23) Write down the steps in implementing a Boolean function with levels of NAND Gates?
24) Give the general procedure for converting a Boolean expression in to multilevel NAND diagram?
24) What are the basic digital logic gates?
26) What is a Logic gate?
27) Which gates are called as the universal gates? What are its advantages?
PART-B
1. Design a 4-bit binary adder/ subtractor circuit.
a) Basic equations. (4)
b) Comparison of equations. (4)
c) Design using twos complement Circuit diagram. (8)
2. Design a half adder using NAND – NAND logic. (16)
3. Explain how a full adder can be built using two half adders. (16)
4. Design a half adder using at most three NOR gates. (16)
5. Using 8 to 1 multiplexer, realize the Boolean function
T = f(w, x, y, z) = Σ(0,1,2,4,5,7,8,9,12,13) (16)
6. Design a 8421 to gray code converter. (16)
7. Draw the logic diagram of full subtractor and explain its operation. (16)
8. Draw the circuit diagram of NMOS NAND gate and explain its operation. (16)
9. a) Design a full adder circuit using only NOR gates. (4)
b) Draw the circuit of a CMOS two inputs NAND gate (12)
UNIT II SYNCHRONOUS SEQUENTIAL CIRCUITS
PART-A
1. What are the classifications of sequential circuits?
2. Define Flip flop.
3. What are the different types of flip-flop?
4. What is the operation of RS flip-flop?
5. What is the operation of SR flip-flop?
6. What is the operation of D flip-flop?
7. What is the operation of JK flip-flop?
8. What is the operation of T flip-flop?
9. Define race around condition.
10. What is edge-triggered flip-flop?
11. What is a master-slave flip-flop?
12. Define skew and clock skew.
13. What are the different types of shift type?
14. Explain the flip-flop excitation tables for T flip-flop
15. Define sequential circuit?
16. Give the comparison between combinational circuits and sequential circuits.
17. What do you mean by present state?
18. What do you mean by next state?
19. State the types of sequential circuits?
20. What are the types of shift register?
PART-B
1) i) Realize a JK flip flop using SR flip flop. (8)
ii) Realize a SR flip flop using NAND gates and explain its operation. (8)
2) Explain various steps in the analysis of synchronous sequential circuits
with suitable example. (16)
3) i) Distinguish between a combinational logic circuit and a sequential (4)
logic circuit.
ii) Derive the characteristic equation of SR flip flop T1 PG 257. (8)
iii) Using a JK flip flop, explain how a D flip flop can be obtained. (4)
4) Design a four state down counter using T flip flop. (16)
5) Design a 4-bit synchronous 8421 decade counter with ripple carry. (16)
6) Design a synchronous 3-bit gray code up counter with the help of
excitation table. (16)
7) Describe the input and output action of JK master/slave flip flops. (16)
8) D(16esign a MOD-10 synchronous counter using JK flip flops
9) Realize SR neither flip flop using NOR gates and explain its operation. (16)
10) a) Design a 3-bit binary up-down counter. (8)
| b) Design a 4-bit UP/DOWN synchronous binary counter. | |
| 11) a)Design a divide by 6 (MOD 6) counter using T flip flop. | |
| b) Realize a D flip flop using SR and T flip flops. |
UNIT III
ASYNCHRONOUS SEQUENTIAL CIRCUITS PART A
1) Define asynchronous sequential circuit?
2) Give the comparison between synchronous & asynchronous sequential circuits?
3) What are the steps for the design of asynchronous sequential circuit?
4) What is fundamental mode sequential circuit?
5) What are pulse mode circuits?
6) What is the significance of state assignment?
7) When does race condition occur?
8) What are the different techniques used in state assignment?
9) What are the steps for the design of asynchronous sequential circuit?
10) What is hazard?
11) What is static 1 hazard?
12) What are static 0 hazards?
13) What is dynamic hazard?
14) What is the cause for essential hazards?
15) What is SM chart?
16) What are the advantages of SM chart?
17) What is primitive flow chart?
18) What is combinational circuit?
19) What is state equivalence theorem?
20) What do you mean by distinguishing sequences?
21) Prove that the equivalence partition is unique
22) Define compatibility.
23) Define merger graph.
PART B
1. Explain with neat diagram the different hazards and the (16)
way to eliminate them.
2. State with a neat example the method for the minimization
of primitive flow table. (16)
3. a) Explain in detail about Races. (6)
b) Explain the different methods of state assignment . (10)
4. a) Explain the fundamental mode asynchronous sequential circuit. (8)
b) Briefly explain the pulse mode asynchronous sequential circuit. (8)
5.What are the steps in the analysis and design of asynchronous
sequential circuits? Explain with an example. (16)
9. Find a circuit that has no static hazards and implements the
Boolean function F(A,B,C,D) = Σ (0,2,6,7,8,,10,12) . (16)
UNIT IV
PROGRAMMABLE LOGIC DEVICES, MEMORY & LOGIC FAMILIES
PART A
1. Explain ROM.
2. What are the types of ROM?
3. What is programmable logic array? How it differs from ROM?
4. What is mask - programmable?
5. What is field programmable logic array?
6. List the major differences between PLA and PAL
7. Why the input variables to a PAL are buffered
8. Why RAMs are called as Volatile?
9. Define RAM.
10. List the two categories of RAMs.
11. Define Static RAM and dynamic RAM
12. Define a bus.
13. Define Cache memory.
14. Give the feature of flash memory.
15. What are Flash memories?
16. What is a FIFO memory?
17. What is programmable logic array? How it differs from ROM?
18. Give the comparison between PROM and PLA.
19 Classify the logic family by operation?
PART B
| 1. | a) Explain the operation of bipolar Ram cell with suitable diagram. | |
| b) Explain the different types of ROM. | ||
| 2. | What is Ram? Explain the different types of RAM in detail. | |
| 3. | Draw the circuit of a NMOS two input NOR gate | |
| and explain its operation. | ||
| 4. | Discuss about the TTL parameters. Draw the TTL inverter circuit. | |
| 5. | a) Draw the circuit of TTL NAND gate and explain its operation. | |
| b) Draw the circuit of NMOS NAND gate and explain its operation. | ||
| 6. | Draw the ECL circuit and explain its operation clearly. | |
| 7. | Explain the totem circuit of TTL logic family. |
UNIT V
VHDL
PART A
1) Write the acronym for VHDL?
2) What are the different types of modeling VHDL?
3) What is a package and what is the use of these packages
4) What is variable class give example for variable?
5) Name two subprograms and give the difference between these two.
6) What is subprogram overloading?
7) Write the VHDL coding for a sequential statement (d-flip-flop ) entity
8) What are the different kinds of the test bench?
9) What is Moore FSM?
10) Write the test bench for and gate entity.
11) Give the different arithmetic operators?
12) Give the different bitwise operators.
13. Differentiate a signal and variable?
14. Explain ‘case’ statement in VHDL with an Example.
15. Explain ‘BLOCK’ statement in VHDL with an Example.
16. Explain ‘Process’ statement in VHDL with an Example.
17. Explain ‘Generate’ statement in VHDL with an Example.
18. What is Test Bench?
19. Give the behavioral model for JK flip-flop.
20. Give the behavioral model for T flip-flop.
PART B
1. Explain the various modeling methods used in VHDL with an example. (16)
2. Explain in detail about the principal of operation of VHDL Simulator. (16)
3. Write the VHDL program for 4 bit counter. (16)
4. Write the VHDL program for full adder in all three types of modeling? (16)
5. Write VHDL program for 4:1 MUX using behavioral modeling. (16)
6. Write VHDL program for encoder and decoder using structural modeling. (16)
7. With an example explain in detail the test bench creation. (16)
8. Write a verilog program for
1) Full Adder. (8)
2) Shift Register. (8)
AUTHOR EEE MS VIDHYA click here to get full Download
Wednesday, May 2, 2012
ELECTROMAGNETIC FIELDS Fourth Semester question banks emf
B.E./B.Tech. DEGREE EXAMINATION, APRIL/MAY 2010
Fourth Semester
Electronics and Communication Engineering
EC2253 — ELECTROMAGNETIC FIELDS
(Regulation 2008)
Time: Three hours Maximum: 100 Marks
Answer ALL Questions
PART A — (10 ï¾— 2 = 20 Marks)
1. State Stoke’s theorem.
2. Define electric scalar potential.
3. State Biot-Savart law.
4. Write down Lorentz force equation.
5. Define dielectric strength of material and give its unit.
6. What do you mean by Magnetization?
7. What is Displacement current density?
8. State Poynting vector.
9. What is skin effect?
10. Define Brewster angle.
PART B — (5 ï¾— 16 = 80
Marks)
11. (a) (i) Given the two points
A(x = 2, y = 3, z = −1) and ( _ _ ) B r = 4, è = 25 , ö = 120 .
Find the spherical co-ordinates of A and Cartesian
Co-ordinates of
B . (8)
(ii) Find curl
H , if ( ) z H
= 2 cos a
− 4 sin a
+ 3a
ñ ö ñ ö ñ ö . (8)
Or
(b) (i) A circular disc of radius ‘a’ m is
charged uniformly with a charge of
ó c/m2. Find
the electric field intensity at a point ‘h’ metre from the
disc along its axis. (8)
(ii) If
+
= + − 2
2
2
4
2 20
x y
V x y z volts, find E
and D
at P(6,− 2.5, 3).
12. (a) (i) State and explain Ampere’s circuital law. (8)
(ii) Find an expression for H at any
point due to a long, straight
conductor carrying I amperes. (8)
Or
(b) (i) Find the maximum torque on an 85 turns, rectangular
coil with
dimension (0.2 ï¾— 0.3)m, carrying a current
of 5 Amps in a field
B = 6.5T . (8)
(ii) Derive an expression for Magnetic vector potential. (8)
13. (a) (i) Derive Poisson’s and Laplace’s equation. (8)
(ii) A parallel plate capacitor has an area of 0.8 m2, separation of
0.1 mm with a dielectric for which = 1000 r
Ã¥ and a field of 6
10 V/m.
Calculate C
and V
. (8)
Or
(b) (i) Derive an expression for the inductance of solenoid.
(8)
(ii) Derive the boundary conditions at an interface between
two
magnetic Medias. (8)
14. (a) (i) Derive modified form of Ampere’s circuital law
in Integral and
differential forms. (8)
(ii) Find the amplitude of displacement current density
inside a
capacitor where = 600 r å and
6
3 10D
= ï¾— − ( 6 ) 2
sin 6 10 0.3464 c/m z
ï¾— t − x a . (8)
Or
(b) (i) Derive Maxwell’s equation derived from Faraday’s law
both in
Integral and point forms. (8)
(ii) In free space, ( ) z H
= 0.2cos wt − âx a A/m. Find
the total power
passing through a circular disc of radius 5 cm. (8)
15. (a) (i) Derive the general wave equation. (8)
(ii) Discuss the wave motion in good conductors. (8)
Or
(b) Explain the reflection of plane waves by a perfect
dielectric. (16)
—————————
Tuesday, May 1, 2012
FOURTH SEMSTER ANNA UNIVERSITY QUESTION BANKS FOR ECE
Probability and Random Processes, Electronic Circuits II,Communication Theory,Electromagnetic Fields,Linear Integrated Circuits,Control Systems,unit 1,2,3,4,5 notes question banks for ece fourth semester
ANNA UNIVERSITY QUESTION BANKS FOR ECE, ECE FOURTH, Anna University Questions Banks, Anna University Chennai Question Bank, QUESTION BANKS, MATHS, ALL DEPT,
ANNA UNIVERSITY QUESTION BANKS FOR ECE, ECE FOURTH, Anna University Questions Banks, Anna University Chennai Question Bank, QUESTION BANKS, MATHS, ALL DEPT,
Probability and
Random Processes
NOTES 3
NOTES 4
NOTES 5
Notes 6
Electronic Circuits II
NOTES 4
NOTES 5
Notes 6
Communication Theory
NOTES 4
NOTES 5
Notes 6
Electromagnetic
Fields
NOTES 2 LECTURE NOTES
NOTES 3
NOTES 4
NOTES 5
Notes 6
Linear Integrated
Circuits(LIC)
NOTES 4 *
Notes 6
Control Systems
NOTES 2 new
NOTES 3
NOTES 4
NOTES 5
Notes 6
EC2251: ELECTRONIC CIRCUITS II QQUESTION BANKS
ANNA UNIVERSITY QUESTION BANKS FOR ECE, ECE FOURTH, QUESTION BANKS, Anna University Chennai Question Bank, Anna University Questions Banks,ELECTRONIC CIRCUITS II - EC2251, OTHERS, FOURTH SEMESTER EC-II NOTES
Anna University
EC2251: ELECTRONIC CIRCUITS II
SEM / YEAR: IV/ II
QUESTION BANK – 2012 Edition
UNIT I
FEEDBACK AMPLIFIERS PART-A
1. Define positive and negative feedback.
2. Define loop gain.
3. List the characteristics of negative feedback amplifiers.
4. Addition of negative feedback to an amplifier reduces its voltage gain from 300 to 60.Determine the feedback factor.
5. What are the different classifications of negative feedback amplifier?
6. How negative feedback causes reduction in noise in amplifiers?
7. Draw the equivalent circuit of a transconductance amplifier.
8. Derive using a block diagram the closed loop forward transfer ratio Af of a feedback system.
9. If an amplifier has a gain of 400and feedback ratio is 0.1,find the gain with negative feedback
10. Compare the input and output resistance for a voltage and current shunt feedback amplifier.
11. Draw a block diagram of voltage shunt feedback feedback amplifier and give its input and output resistance.
12. What are the disadvantages of negative feedback?
13. How negative feedback reduces distortion in an amplifier?
14. Define feedback factor.
15. What are the advantages of negative feedback in amplifier.
16. Define desensitivity of transfer gain.
17. Determine the gain of an amplifier with feedback,when the open loop gain is 200 and the feedback factor is 0.2.
18. Determine the gain with feedback for the amplifier with the open loop and feedback factor 0.1.
19. Identify the type of feedback of the circuit shown:
PART-B
1. Draw the circuit of a current series feedback amplifier and explain . Derive expressions for input and output impedance.
How does it improve the stability of the amplifier. (16)
2. (i) Draw the block diagrams of the four possible feedback topologies and explain. (6)
(ii) Prove that the bandwidth of the amplifier increases with negative feedback. (10)
3. (i) Show how negative feedback reduces gain of an amplifier. (8)
(ii) Explain the effect of negative feedback on the input resistances for a voltage shunt feedback amplifier. (8)
4. Explain the working of voltage series feedback amplifier with circuit diagram and small signal equivalent circuit. Derive the expressions for voltage gain, input impedance and output impedance. (16)
5. (i) Draw the circuit diagram and equivalent circuit for current shunt feedback amplifier and derive the expression for total voltage gain. (10)
(ii) what are the different performance measures of feedback amplifiers? Discuss each in brief. (6)
6. (i)What is the effect of negative feedback on the bandwidth and distortion of an amplifier. (10)
(ii) A negative feedback is used to reduce the noise from an amplifier by 80%.Waht must be the percentage negative feedback to accomplish this if the amplifier voltage gain is 100? (6)
7. Draw the circuit of an emitter follower. Identify the type of negative feedback.calculate the gain, input and output resistance with and without feedback. (16)
8. Describe with necessary derivations, discuss the effects of negative feedback amplifier. (16)
9. (i) Discuss the classification of feedback amplifiers with schematic (topology).How is impedance level modified in each type? (8)
(ii) Derive expression for Avf with positive and negative feedback and state condition for stability in negative feedback amplifiers. (8)
UNIT-II
OSCILLATORS
PART A
1. What is oscillator?
2. What are the classifications of Oscillators?
3. What are the factors which affect the frequency stability of an oscillator?
4. Draw the equivalent circuit of a quartz crystal.
5. A wein bridge oscillator is used for operation at 10KHz . If the value of the resistance R is 100 K ohms , what is the value of C required.
6. Define Barhausen Criterion.
7. What are the types of feedback oscillators?
8. What are the conditions for oscillation?
9. Define Piezoelectric effect.
10. Draw the equivalent circuit of crystal oscillator.
11. What is Miller crystal oscillator?
12. State the frequency for RC phase shift oscillator.
13. What is Q factor?
14. What is dissipation factor?
15. Draw the electrical equivalent circuit of crystal and mention the significance of each component.
16. Draw the Miller’s oscillator circuit.
PART B
1. Describe Hartley oscillator with neat circuit diagram . Determine the frequency of oscillations and the oscillation condition for it. (16)
2. Write short notes on
(i)Milter oscillator (8)
(ii) Crystal oscillator (8)
3. (i)Sketch the circuit and explain the operation of a RC phase shift oscillator .Derive the expression for frequency and condition for sustained oscillations for the circuit. (12)
(ii)Explain the need for three RC networks for the circuit functioning. (4)
4. With a neat circuit diagram ,explain the operation of a transistor pierce crystal oscillator. (16)
5. Explain the principle of operation of a wein bridge oscillator. (16)
6. Draw the amplitude and phase conditions that are to be satisfied in LC oscillators using pi network.Hence obtain the frequency of oscillator of a Hartley oscillator. (16)
7. (i)With circuit diagram drive an expression for frequency of oscillation of a Clapp oscillator .Explain how Barhausen conditions are satisfied. (8)
(ii) Bring out the advantages of Clapp oscillator over Colpitt oscillator. (8)
1. What are the advantages of tuned amplifiers?
2. What are the disadvantages of tuned amplifiers?
3. What is neutralization?
4. What are double tuned amplifiers?
5. What is a stagger tuned amplifier?
UNIT III
TUNED AMPLIFIERS
PART A
6. What are the advantages of double tuned over single tuned?
7. What are the different types of neutralization?
8. What is rice neutralization?
9. What is unloaded Q?
10. What are the different coil losses?
11. A tuned amplifier is designed to receive A.M. broad cast of speech signal at 650kHz. What is needed Q for amplifier?
12. Why neutralization is used in tuned amplifiers?
PART B
1. (i)Explain the effect of changing Q of the coil used in tank circuit on its bandwidth. (8)
(ii) Derive the equation for 3 dB bandwidth of capacitance coupled single tuned amplifier. (8)
2. (i)What is stagger tuned amplifier? Explain its working. (8)
(ii)Write brief notes on Hazeltine neutralization.
3. Define Quality factor.Obtain the quality factor for a parallel resonant circuit. (16)
4. (i)Explain the working and frequency response of a single tuned amplifier circuit. (12)
(ii)What are synchronous and stagger tuned amplifier circuits. (4)
5. With circuit diagram and waveforms explain the operation of a Schmitt trigger circuit using two transistors for a sinusoidal input. (16)
6. (i)Draw a class c tuned amplifier and drive its efficiency. (8)
(ii)Describe any one method of neutralization used in tuned amplifier. (8)
7. (i)Draw the single tuned amplifier and explain the frequency response. (6)
(ii)Drive the expression for its gain and cutoff frequency (6)
(iii)What is meant by synchronous tuning of tuned amplifier. (4)
UNIT-IV
WAVE SHAPING AND MULTIVIBRATOR CIRCUITS
PART A
1. What is multivibrator?
2. Name the types of Multivibrators?
3. How many stable states do bistable Multivibrator have?
4. What are the applications of bistable Multivibrator?
5. What are the different names of bistable Multivibrator?
6. Why is monostable Multivibrator called gatting circuit?
7. Why is monostable Multivibrator called delay circuit?
8. What is the main characteristics of Astable Multivibrator?
9. What is the other name of Astable Multivibrator- why is it called so?
10. What are the two types of transister bistable Multivibrator?
11. How are the values R1, R2 and VBB chosen in bistable Multivibrator?
12. What is self biased Multivibrator?
13. What are the other names of speed up capacitors?
14. Define transition time.
15. Define resolving time.
16. Define gate width.
17. What are the advantages of monostable Multivibrator?
18. What are the applications of astable Multivibtrator?
19. What is a complementary Multivibrator?
20. What is the important application of Schmitt trigger?
PART B
1. (i)Explain the working principle of complementary collector coupled astable multivibrator. (8)
(ii)With neat circuit diagram, explain the operation of bistable multivibrator. (8)
2. (i)Describe the different triggering methods used for multivibrator circuits. (8)
(ii)Draw and explain Schmitt trigger circuit and also draw the its waveform. (8)
3. (i)Draw the circuit of a collector coupled transistor monostable multivibrator.Sketch the waveforms at base and collector for each transistor when the circuit is trigerred and explain its working. (10)
(ii)Explain circuits used to trigger a transistor monostable multivibrator circuit. (6)
4. Design a Schmitt trigger circuit for Vcc=10 V;UTP=5 V;LTP=3V.Assume hfe=100 and Ic=1 mA. (16)
5. Design a monostable multivibrator for the following specifications:Vcc=10 V;Vbb=6V;Ic=1 mA;duration of output pulse=14 sec;hfe min=100;Icbo=0;Vbe=-0.5 V. (16)
6. (i)Explain the working of emitter coupled astable multivibrator with a circuit diagram and derive for its frequency. (8)
(ii)Design the collector coupled astable multivibrator using Vcc=20V and Ic sat= 3 mA to generate a pulse wave at f=2 kHz with 70% duty cycle. (8)
UNIT V
BLOCKING OSCILLATORS AND TIMEBASE GENERATORS
PART A
1. Define Blocking Oscillator.
2. What are the two important elements of Blocking Oscillator?
3. What are the applications of blocking Oscillator?
4. Give the expression for co-efficient of coupling.
5. Give the formula for transformation ratio.
6. Define rise time.
7. Define overshoot.
8. Define flat top response.
9. Define droop or a tilt.
10. What are the applications of pulse transformer.
11. When do the core saturates?
12. What are the two types of astable Blocking Oscillator?
13. Define Sweeptime in sawtooth generator.
14. Define Displacement error in the sawtooth generator.
15. What is constant current charging?
PART B
1. (i)Explain how blocking oscillator can be used to generate high current pulses of short duration. (8).
(ii)Explain the applications of voltage and current time base circuits. (8)
2. (i)Give the circuit diagram of milter saw tooth generator and explain its working with necessary waveforms. (8) (ii)Write brief notes on monostable blocking oscillator.
3. With a neat diagram explain the circuit for generating sweep using UJT.Obtain the expressions for sweep period and frequency. (16)
4. Explain the operation of a bootstrap ramp generator circuit.Discuss the advantages of this circuit with other ramp generators. (16)
5. (i)With circuit diagram explain the operation of a linear voltage time base generator. (8)
| 6. | (i)Explain the working of a free running blocking oscillator. (ii)How a high pass RC circuit is used as a differentiator? | (8) (8) | |
| (ii)Obtain the period of oscillation of a UJT relaxation oscillator. | (8) | ||
| 7. | Explain bootstrap saw-tooth generator with circuit diagram and draw the output signal. | (16) | |
| 8. | (i)Describe Monostable blocking oscillator using base timing. | (8) | |
| (ii)Explain UJT sawtooth generator in detail. ANNA UNIVERSITY QUESTION BANKS FOR ECE, ECE FOURTH, QUESTION BANKS, Anna University Chennai Question Bank, Anna University Questions Banks,ELECTRONIC CIRCUITS II - EC2251, OTHERS, FOURTH SEMESTER EC-II NOTES | (8) |
Subscribe to:
Posts (Atom)
.jpg)
